Hardmasks are employed as etch masks for a variety of semiconductor manufacturing processes. Titanium nitride (TiN) hardmasks have been used, for example, for forming self-aligned vertical interconnect accesses (VIAs) (the simultaneous formation of a layer metal (metalx) pattern and Via levels (Vx) VIAs). However, TiN hardmask layers have poor etch resistance, particularly at the edge of the wafer. The poor etch resistance prevents the hardmask layers from being used in processes related to, for example, trench first metal hardmask schemes, VIA double patterning schemes and merged VIAs, such as two, three, four and above numbers of merged VIAs.
A need therefore exists for methodology enabling hardmask layers with lower residual stress for enhanced etch resistance and hardness, and the resulting device.